1. Field of the Invention
The present invention relates to a signal transmission apparatus with a plurality of LSIs (Large Scale Semiconductor Integrated Circuit) which is capable of transmitting a data signal at high speed between a first LSI and a second LSI of the signal transmission apparatus in case that the first LSI and the second LSI are operated by a common reference clock signal and that the data signal outputted from the first LSI is received and processed by the second LSI.
2. Description of the Related Art
Various kinds of electronic appliances and/or devices have been highly advanced and have been large scaled, and many LSIs are used in one apparatus and the high speed operation of such apparatus is requested. In addition, for example, as in a semiconductor device testing apparatus, it is sometimes requested to operate many LSIs used in the testing apparatus by the same reference clock signal and to cause the LSIs to process respective data signals at the same timing. In this case, as shown FIG. 1, a reference clock signal from a clock source 11 is supplied to distribution means 13 in which a plurality of buffers 12 are connected in tree structure and is distributed by the distribution means. These distributed reference clock signals are supplied to LSIs 14, 15, . . . through buffers 12 of the same number of stages, respectively. In FIG. 1, only two LSIs are shown, but usually many LSIs are used. In each of the LSIs 14 and 15, the supplied reference clock signal is sent to distribution means in which a plurality of buffers 16 are connected in tree structure. Then, the reference clock signal is distributed to various parts or portions from the central portion of each of the LSIs 14 and 15 via the buffers 16 of the same number with one another to make the internal clock signals of the same phase. The data signals in the LSIs are processed at the same timing using those internal clock signals, respectively.
For example, in the LSI 14, a data signal 18 is taken in a flip-flop 17 by an internal clock signal and the data signal taken in the flip-flop 17 is outputted to the outside through a buffer 19. The data signal 21 is supplied to the LSI 15 via a signal line 22 and is taken in a flip-flop 24 by the internal clock signal through a buffer 23 in the LSI 15.
The reference clock signal from the clock source 11 must be distributed to many paths. Also, a relatively large phase difference is generated between the reference clock signals inputted to the LSIs 14 and 15 because of the relationship of the arrangement of many LSIs. As a result, it is difficult to transmit data signals at high speed. That is to say, for example, as shown in FIG. 2, assuming that the input data signal 18 (FIG. 2A) of the flip-flop 17 in the LSI 14 is taken in the flip-flop 17 by the internal clock signal CK.sub.1 (FIG. 2B) of the LSI 14 and the output data signal 21 from the LSI 14 becomes as shown in FIG. 2C, and that the internal clock signal CK.sub.2 of the LSI 15 is delayed by time t.sub.1 relative to the internal clock signal CK.sub.1 as shown in FIG. 2D due to the relative delay of the distributed reference clock signal, the data signal taken in the flip-flop 24 becomes as shown in FIG. 2E. If the time required to set up a data signal in the flip-flop 24 to the internal clock signal is t.sub.s and the dispersion of the internal clock signal CK.sub.2 based on the dispersion of LSI pattern to the internal clock CK.sub.1 is t.sub.u, since the data signal cannot correctly be taken in the flip-flop 24 for the input data change during the set-up time t.sub.s, the data signal cannot correctly be taken in the flip-flop 24 when the value t.sub.a which is the value that the delay time t.sub.1, the set-up time t.sub.s and the dispersion time t.sub.u are subtracted from the period T.sub.0 of the reference clock signal is not positive. The set-up time t.sub.s and the dispersion time t.sub.u are the fixed values. If t.sub.1 is large and the period T.sub.0 is small due to the high speed data signals, t.sub.a =(T.sub.0 -t.sub.1 -t.sub.s -t.sub.u) becomes zero or a negative value and thus the data signals cannot be transmitted. Particularly, the phase difference t.sub.1 between the reference clock signals distributed to the LSIs mounted on the different wiring substrates is considerably large and thus, the transmission of the high speed data signals is difficult.
In order to solve this problem, in the prior art, as shown in FIG. 4 where the same reference characters are assigned to the portions corresponding to those of FIG. 1, delay lines 25 and 25' are inserted into the reference clock distribution means 13 for LSIs 14 and 15, respectively, to adjust each delay amount of the delay lines 25 and 25' so that the phases of the clock signals reaching the respective LSIs 14 and 15 are the same.
However, there is a shortcoming that the provision of such delay lines 25 and 25' makes the space of the printed circuit substrate (board) large and the adjustment of the delay of the delay lines 25 and 25' requires long time.
In addition, an LSI operating at a frequency of several hundred MHz has appeared and the reference clock signal whose period is several nano seconds has been requested. In such a high speed transmission, if the LSIs 14 and 15 are mounted on the same printed circuit substrate, the signal line 22 connecting between the LSIs 14 and 15 has a reduced allowance in its wiring pattern length. For example, if the data signal taken in the LSI 14 is outputted from the LSI 14 with the delay time t.sub.2 as shown in FIG. 3B against the reference clock signal CK.sub.S (FIG. 3A) distributed to LSIs 14 and 15, the difference t.sub.b between the clock period T.sub.0 and the sum of the delay time t.sub.2, the set-up time t.sub.s and the dispersion time t.sub.u is the delay time permitted for the signal line 22 between the LSIs 14 and 15. Namely, the delay time of the signal line 22 is required not to be longer than the time t.sub.b. If t.sub.b is 4 nano seconds, the signal line (wiring pattern length) 22 cannot be longer than approximately 10 cm.
In order to improve this problem, a circuit called an interleave system has been used. That is, as shown in FIG. 4, the internal clock signal CK.sub.1 of the LSI 14 is frequency divided into one second (1/2) frequency by a frequency divider circuit of a flip-flop 26. As the Q output and the Q output of the flip-flop 26, two series of low speed clock signals CKa.sub.1 and CKb.sub.1 each period of which is mutually shifted by the period of the internal clock signal CK.sub.1 and is two time length of the internal clock CK.sub.1 are obtained. The output data (FIG. 5C) of the flip-flop 17 are taken by the rising edges of these low speed clock signals CKa.sub.1 and CKb.sub.1 in the flip-flops 27 and 28, respectively, as shown in FIGS. 5F and 5G. That is, each of the data D.sub.1, D.sub.3, D.sub.5, . . . is outputted from the flip-flop 27 in double length and each of the data D.sub.2, D.sub.4, D.sub.6, . . . is outputted from the flip-flop 28 in double length. These data of reduced speed from the flip-flops 27 and 28 are outputted from the LSI 14 and supplied to the LSI 15 via the signal lines (wiring patterns) 22a and 22b. In the LSI 15, the internal clock signal CK.sub.2 is frequency divided into one second frequency by a frequency divider circuit of a flip-flop 31 to obtain the same signals as shown in FIGS. 5D and 5E as the Q output and the Q output respectively. The data from the signal lines 22a and 22b are taken in the flip-flops 32 and 33 by the rising edges of the respective low speed clock signals. The output data of the flip-flops 32 and 33 are controlled by the Q output of the flip-flop 31 in a multiplexer 34 and alternately taken out in the period of the internal clock CK.sub.2. Then the data are supplied to flip-flop 24.
In this case, as is apparent from FIG. 5, the delay time in the signal lines 22a and 22b is permitted up to the difference between 2T.sub.0 and the sum of the data signal delay time t.sub.2 in the LSI 14, the set-up time t.sub.s and the dispersion time t.sub.u. That is, approximately time T.sub.0 more allowance could be provided than the case of FIG. 1. In the above case, the data signals are converted into two series of low speed data signals by making the period double and are transmitted. However, in general, high speed data signals are transmitted by converting the data into N (N is an integer equal to or greater than 2, particularly, 2.sup.1, 2.sup.2, 2.sup.3, etc.) series of low speed data signals having N time period and by similarly transmitting them.
However, when an LSI is organized utilizing so called ASIC (Application Specific IC) which comprises arrays of basic units (basic cells) such as gates and is constructed as a special purpose circuit based on a user request, the circuit of FIG. 4 requires four times of the number of flip-flops compared with the circuit of FIG. 1. In the above example, the data transmission in bit basis is shown. However, 16 bit data or 32 bit data are usually transmitted and in this case, the signal transmission systems shown in FIG. 1 or FIG. 2 must be provided in parallel for the number of bits. The interleave system shown in FIG. 4 requires significantly more basic cells in the ASIC. Thus, there is a problem that the number of basic cells for other functions in the ASIC is limited.
Therefore, a first object of the present invention is to provide a signal transmission apparatus with a plurality of LSIs which is capable of a high speed data signal transmission between a plurality of LSIs mounted on a printed wiring substrate or on different printed wiring substrates, which mutually sends and receives data signals and operates with a reference clock signal without requiring a phase adjustment requiring long time and without requiring a large scale hardware, i.e. a large space on the wiring substrate.
A second object of the present invention is to provide a signal transmission apparatus with a plurality of LSIs which is capable of a high speed data signal transmission between a plurality of LSIs mounted on a printed wiring substrate, which operates by a reference clock signal and mutually sends and receives data signals with the reduced number of basic cells and with an increased allowance for the signal line length (wiring length) between the LSIs.
A third object of the present invention is to provide a signal transmission apparatus with a plurality of LSIs which satisfies the first object and the second object at the same time.